1. Field of the Invention
The present invention generally relates to the manufacture of semiconductor devices and, more particularly, insulating and passivation layers thereof.
2. Description of the Prior Art
Advances in processes for manufacture of semiconductor devices now permit millions of circuit elements such as capacitors for dynamic memories and transistors for logic arrays to be formed on a single chip. Many of these advances have been made possible through improvements in process control since the conditions under which desired structures are formed may adversely affect previously formed structures.
For example, impurities may be located with substantial precision within a volume of semiconductor material by control of implantation processes and are generally diffused slightly during subsequent annealing at elevated temperature for a short period of time. Compensation for this diffusion can generally be made by the initial location of the implant so that the diffusion during carefully controlled heat treatment achieves the desired location of the impurities. The heat treatment also serves to repair damage to the crystal lattice structure caused by the implantation process by annealing.
However, further heat treatment subsequent to annealing may cause further diffusion which is not desired. Any such further diffusion becomes particularly critical as the sizes of structures forming electronic elements is reduced to obtain higher integration densities and high performance of transistors. Oxide growth may also occur at insulator interfaces through similar mechanisms of material diffusion. Accordingly, an aspect of integrated circuit design is referred to as a heat budget which must not be exceeded if fabrication of the integrated circuit device is to be successfully accomplished. Maximum temperatures are also imposed by some structures which cannot be exceeded after the structures are formed.
Integrated circuits including a large plurality of individual circuit elements also require those elements to be interconnected as well as connected to other structures (e.g. connection pads) for supplying power and input signals to the chip and extracting output signals from it. Such connections are generally made to overlie the circuit elements on the chip and therefore must be insulated therefrom except where connections are to be made.
The integrity and reliability of such connections may be compromised if the topology which the connections must traverse is severe. For these circuit elements, a silicate glass (SiO.sub.2) is normally used as an insulator between metal line interconnections or in shallow trench isolation structures. In addition to conventional silicate glass, phosphorus is added as a dopant to provide alkali (Na, K, Li) gettering capability in the pre-metal dielectric (PMD) layer. Dopant concentrations of 2%-4% by weight of phosphorus are required to getter alkali elements. In the resulting phosphosilicate glass (PSG) layer, the addition of dopant also softens the silicate glass and provides an enhanced reflow characteristic under high temperature annealing conditions.
Accordingly, a common structure in the fabrication of integrated circuits is a so-called passivation layer, which is generally formed of a phosphosilicate glass film after electronic element structures are completed. To reduce severity of topology of the surface, it is necessary to fill surface discontinuities such as trenches or gaps between portions of a patterned layer without creating voids in the insulating layer which may cause metal shorts in metal layers deposited after the contact opening process.
Since trenches and gaps under current design rules may have a relatively high aspect ratio (e.g. 4:1 or greater ratio of depth to width) and be quite narrow (e.g. 0.2-0.1 .mu.m or less), filling them is difficult. Failure to adequately fill such trenches and gaps is very likely to cause a major adverse impact on manufacturing yield either by creation of voids or failure to reduce severity of surface topology which compromises metal conductors. Voids are generally due to more rapid deposition at the top of a trench or gap than at the bottom, closing or restricting delivery of material to lower portions of the trench before it can be filled.
The insulator material must also be as dense as possible as deposited to provide a stable film that does not absorb atmospheric moisture. High film density thus avoids a post-deposition densification annealing step in forming the layer. High film density may also develop a high dielectric constant. However, as device spacings and film thicknesses are reduced, a high dielectric constant corresponding to suitable film density for good film stability may also increase capacitive coupling between conductors and becomes a source of noise susceptibility. Therefore, as will be discussed below, control of dielectric constant is becoming of increased importance in modern integrated circuit design.
To improve gap filling of fill material, silicate and phosphosilicate glass films are often deposited with boron doping (using a source such as triethylborate) to further reduce the viscosity of the glass so that these films can possibly flow (depending on temperature) both during deposition and/or during post-deposition annealing or thermal cycling. For shallow trench isolation (STI) applications, however, such doping is inappropriate due to the potential out-diffusion of boron to nearby device junctions. Where boron doping can be used, however, with moderate (4%-5% by weight) levels of boron doping, these films reflow after a thirty minute anneal at temperatures above 800.degree.-850.degree. C. and narrow gaps of aspect ratio in the range of 3:1-4:1 can be filled without voids. However, attempts to use a boron doping level in excess of 5% in combination with a 4%-5% phosphorus concentration are not successful due to instability of such highly doped films and defects that result therefrom.
Borophosphosilicate glass (BPSG) films may be deposited using tetraethylorthosilicate (TEOS), oxygen or ozone, a phosphorus source such as PH3, triethylphosphate (TEPO), triethylphosphite or trimethylphosphite and a boron source such as B.sub.2 H.sub.6 or triethylborate. Temperatures of either 350.degree.-450.degree. C. or 800.degree.-850.degree. C. have been used for the deposition. Although the higher temperature range provides some reflow during deposition, subsequent annealing at 800.degree.-850.degree. C. is still required to provide void-free gap fill at aspect ratios of 3:1-4:1.
However, the temperature and duration of this anneal/reflow process allows only a small process window or tolerance within the heat budget for some types of integrated circuits such as some dynamic random access memories (DRAMs) and is wholly incompatible with some CMOS devices and logic arrays which may be limited to temperatures below 650.degree. C. Additionally, for some recent logic array designs and CMOS devices in particular, boron has been observed to be an unacceptable contaminant at the pre-metal dielectric (PMD) level due to its effect on gate oxide threshold voltage.
Some variations in materials and thermal processing have been attempted to reduce the thermal cycle for producing a silicon dioxide or glass insulating layer but have only resulted in slight increase of the process window, at most. For example, published European Patent application 0562625 A2 by Imai teaches deposition of a fluorine doped borophosphosilicate glass (BPSG) film by sub-atmospheric pressure CVD at 350.degree.-450.degree. C. using fluorotriethoxysilane (F-TEOS) which requires a subsequent 850.degree. C. reflow/anneal for 30 minutes rather than at 900.degree. C. to achieve a desired reflow surface angle for adequate planarization. Such temperatures clearly remain unsuitable for developing pre-metal passivation layers for CMOS logic arrays as noted above and, for other types of devices, the slight increase in the process window generally does not justify the increase in material cost and process complexity by significant improvement in manufacturing yield.
Multi-step plasma deposition/etch processes have also been developed to fill sub-half micron gaps up to aspect ratios of 1.5:1. In addition to the limited range of aspect ratio, these processes suffer from low throughput and foreign material contamination and risk of causing damage to underlying gate oxide due to plasma charging.
Similarly, reduction of the anneal temperature to 650.degree. C. or less in accordance with the maximum temperatures for further processing of circuits including some types of CMOS devices has limited the aspect ratio at which void-free trench or gap filling can be achieved to about 1.5:1 regardless of dopant content. In general, the need to fill higher aspect ratio structures becomes more critical to meet the application of merged logic and DRAM on a single chip. In such an application, the minimum aspect ratio is at least 2:1. Accordingly, it is seen that known techniques and materials suitable for depositing an insulating layer over some CMOS logic devices are not suitable for dynamic memories and vice-versa although it is desirable to provide both such structures on a single chip. Additionally, modern and advanced CMOS integrated circuit designs include some narrow, high aspect ratio features which cannot be adequately filled by known processes.
Further, while addition of fluorine into BPSG may be effective to reduce viscosity somewhat and may also be desirable to reduce dielectric constant (e.g. to control parasitic capacitances, as alluded to above), little fluorine will be incorporated if the temperature during deposition is too high (above 750.degree. C. Thus the amount of incorporated fluorine will be small. For example, deposition at 750.degree. C. or higher limits fluorine content to 0.1% or less. Therefore for many sources of fluorine such as fluoroethoxysilane (F-TEOS), deposition must be done at low temperatures which prevents high density from being developed in the as-deposited film and the low temperature deposition must be followed by a high temperature anneal/reflow process to achieve gap filling and increase density. Again, temperatures below 650.degree. C. do not provide adequate gap filling of narrow or high aspect ratio gaps or trenches while higher temperatures are unsuitable for modern CMOS devices.
Many different methods of material deposition generally suitable for depositing silicon dioxide are known but fall short of providing a solution to high-aspect ratio gap-filling within necessary heat budgets and maximum temperatures. For example, in addition to the methods discussed above, plasma enhanced chemical vapor deposition (PECVD) has been extensively investigated for formation of passivation films. Gap-filling capability of a single step PECVD process (e.g. without reflow) is limited to about 1.5:1. Further, use of a plasma can cause charging of structures by irregularities of the plasma which can damage electronic structures such as gates of field effect transistors.
PSG and BPSG films may be deposited in either thermal CVD (THCVD) or plasma enhanced CVD (PECVD) reactors. However, while either a THCVD or PECVD PSG or BPSG may be used to fill low aspect ratio (e.g. less than 1:1) features without voids, at higher aspect ratios the gap filling capabilities of PECVD and THCVD processes diverge dramatically due to fundamental differences in the natures of these processes.
In PECVD, reactants are ionized and dissociated in the gas phase by collisions with energetic electrons. The gas mixture presented to the wafer surface has many more species than in the case of THCVD due to the vigorous decomposition of the initial gas by high energy electron bombardment. As a result of the highly energetic gas phase species, species collide with the surface with near unit probability of sticking and reacting. Thus step coverage in PECVD is usually poor and closure is usually observed at the tops of gaps requiring filling while voids are left lower in the gaps.
In contrast, in THCVD, less energetic species have a lower probability of being deposited at the location of first collision with a surface and either lower or higher conformality than PECVD may result, depending on the species to be deposited and the deposition conditions. Additionally, less energetic gas phase reactions that may result in desirable intermediates crucial in achieving a particular result such as void-free gap fill may be produced which are not available from PECVD processes.
Furthermore, while THCVD may be practiced from mTorr pressures to atmospheric pressures (760 Torr) and above, PECVD is usually limited to a regime below 20 Torr due to the difficulty in maintaining a plasma at greater pressures. In addition, while similar reactant species may be used in both PECVD and THCVD systems, as a result of differences noted above, thin films deposited by PECVD have different stoichiometries, stress and stability. Therefore, results achievable with PECVD may not be achieved with THCVD and vice-versa.
Liquid phase deposition (LPD) such as depositing silicon dioxide or fluorinated silicon dioxide from a saturated solution of hydrofluorosilicic acid also develops a low density film. While this process can be conducted at even lower temperatures than PECVD, annealing is required to improve density of deposition for film stability. However, void-free gap filling of the as deposited film is limited to aspect ratios of about 1:1.
Multi-step deposition and etch back processes have been attempted using phosphorus doped TEOS and ozone SACVD at 600 Torr for developing interlevel dielectric fill at sub-quarter micron regimes. All of these multi-step deposition and etch back processes use reactive ion etching which subjects the substrate to potential device damage due to electrical charging. This damage is detrimental to advanced logic and DRAM devices where gate oxide thicknesses may be as low as 50 Angstroms or less. Furthermore, even with such multi-step processes, small voids are not reliably prevented.
Accordingly, no known process provides adequate gap fill of features having a width of less than 0.2 microns with an aspect ratio greater than about 3:1 using a processing temperature below 650.degree. C., maintaining the potential benefits of THCVD, or provides a dense and stable film, as deposited, which may be undoped or doped as desired with phosphorus, fluorine or a combination thereof or which provides such gap filling without boron doping while being compatible with boron doping in appropriate circumstances of semiconductor device design to further extend gap filling capabilities.